[CCoE Notice] Seminar - Dr. Lan Wei - Thursday, Aug. 9 at 10:15 AM

[Fisher, Esmeralda]

Thursday, August 9, 2012
N355-D - 10:15 AM
Nanoelectronics - Device and Circuit Interactive Design and Optimization
Dr. Lan Wei
Microsystems Technology Laboratories, Massachusetts Institute of Technology

Abstract: Nowadays, physical gate length can no longer be effectively scaled down and traditional boosters (e.g., strain, high-k/metal gate) are having diminishing return.  Continued progress in nanoelectronics necessitates a holistic view across the boundaries of device, circuit and system. Device engineering and circuit design must be interactively explored targeting improvement at circuit and system level, while the new applications in various areas are enabled by emerging technology.
In this talk, the design space is explored for future Si CMOS technology, and carbon nanotube field effect transistor, a promising technology in the post-Si era.  Compact models of transport properties and capacitive components of different device structures have been developed to fascinate circuit-level analysis and system-level optimization.  Opportunities and challenges are discussed along the path of continuing technology scaling.  Possible ways of extending technology roadmap are proposed.  We propose scenarios of selective device structure scaling that will enable Si CMOS technology scaling for several generations beyond the currently perceived limits.  Beyond Si CMOS scaling, carbon nanotube field effect transistors (CNFETs) are optimized and projected to achieve 5x chip-level speed up over PDSOI with the same power constraints at 11 nm technology node for a high-performance four-core processor with 1.5M logic gates and 5MB SRAM per core.  A new benchmarking methodology for an apples-to-apples comparison among different device structures is proposed, which also links the device-level behaviors and circuit-level performance and energy efficiency.  The methodology is further extended into an optimizing tool for device/circuit interactive design.

Short Bio:

Lan Wei received her B. S. in Microelectronics and Economics from Peking University, Beijing, China in 2005 and M. S. and Ph. D. in Electrical Engineering from Stanford University, Stanford, USA in 2007 and 2010, respectively. She is currently a post-doctoral associate in Microsystems Technology Laboratories, Massachusetts Institute of Technology. Her research focuses on technology scaling from circuit-level and chip-level perspectives, device/circuit interactive design, as well as integrated bio-system. She worked as a research intern at Intel (2006), IBM Research (2007), STMicroelectronics (2008), and the Grenoble Institute of Technology (2008).
Lan has authored or co-authored more than 30 technical papers.  She has served on the Technical Program Committee of the International Electron Devices Meeting (IEDM) since 2011, and has been a reviewer for several IEEE and ACM journals since 2006.  She was one of the key contributors to the Process Integration, Devices, and Structures (PIDS) Chapter of the International Technology Roadmap for Semiconductors (ITRS) 2009 Edition.




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