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<b><span style="font-size:18.0pt;font-family:"Times New Roman",serif;color:#C8102E">FPGA Implementation and Optimization of Bit Flipping Encapsulation Algorithm for Post Quantum Cryptography in Embedded Systems Applications
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<b><span style="font-size:13.5pt;font-family:"Times New Roman",serif;color:black;mso-ligatures:none">Muhilan Ravindran</span></b><span style="font-size:11.0pt;font-family:"Times New Roman",serif;mso-ligatures:none"><o:p></o:p></span></p>
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<span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;mso-ligatures:none">April 28, 2025, 9 a.m. to 10 a.m. (CST)<br>
Location: </span><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;color:black"><a href="https://urldefense.com/v3/__https://uh-edu-cougarnet.zoom.us/j/84337659578?pwd=KDjOJc7rKPjppDIhvicZTgaxYvB6RN.1__;!!LkSTlj0I!H5--wjGCT105bpeX3i0JavGt2-r5YosivATF4VZnKMUTN2iCZgWNEdI-OvjCU3uaSFjL-n0UYBrNW0yf9nyD1WoE5q0$"><span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:#467886;mso-ligatures:none">Zoom
Link</span></a></span><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-ligatures:none"><o:p></o:p></span></p>
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<b><span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;mso-ligatures:none">Committee Chair:</span></b><span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;mso-ligatures:none"><br>
Dr. Yuhua Chen, DSc. </span><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-ligatures:none"><o:p></o:p></span></p>
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<b><span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;mso-ligatures:none">Committee Members:</span></b><span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;mso-ligatures:none"><br>
Dr. Jinghong Chen, Ph.D. | Dr. Harish Sarma Krishnamoorthy, Ph.D. </span><span style="font-size:10.5pt;font-family:"Aptos",sans-serif;mso-ligatures:none"><o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><b><span style="font-family:"Arial",sans-serif;color:#C8102E;mso-ligatures:none">Abstract</span></b><span style="font-family:"Arial",sans-serif;color:#C8102E;mso-ligatures:none"><o:p></o:p></span></p>
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<span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black">The expeditious advancement of quantum computing has created a threat to classic cryptographic systems, calling for post-quantum cryptography (PQC) solutions like Bit Flipping Key Encapsulation
(BIKE) algorithm, which utilizes Quasi-Cyclic Moderate Density Parity-Check (QC-MCPC) codes for a secure key exchange. Even though BIKE has cryptographic strengths like structural simplicity, and compact key sizes, it suffers from high dynamic power consumption
due to its computationally intensive modular arithmetic operations, which include polynomial multiplication, inversion, and hashing. These factors limits its FPGA implementation for embedded and IoT applications.
</span><span style="font-size:10.5pt;font-family:"Arial",sans-serif"><o:p></o:p></span></p>
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<span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black">This research work presents a resource-constrained FPGA implementation of BIKE on the Artix-7 FPGA, designed for integration into an IoT temperature sensor system on the STM32 microcontroller.
This work focuses on basic design algorithms such as shift and XOR for polynomial multiplication, Itoh-Tsujii for polynomial inversion, validated through complete simulation of BIKE’s key operations such as key generation, encapsulation, and decapsulation.
Although the current implementation focuses on generating a single set of keys and ciphertext per run, it lays a solid foundation for scalable, power-efficient enhancements in the future. This work underscores that even with restrained resources, BIKE can
be made realistic, bridging the gap between PQC and real-world embedded systems deployment.</span><span style="font-family:"Aptos",sans-serif;mso-ligatures:none"><o:p></o:p></span></p>
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