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<p class="MsoNormal"><span style="font-size:13.5pt;font-family:"Arial",sans-serif;color:black"><img width="599" height="171" style="width:6.2395in;height:1.7812in" id="Picture_x0020_2" src="cid:image001.png@01DB9F70.CD8A7B80" alt="Dissertation Defense Announcement at the Cullen College of Engineering"></span><span style="font-size:13.5pt;font-family:"Arial",sans-serif;color:black;mso-ligatures:none"><o:p></o:p></span></p>
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<b><span style="font-size:18.0pt;font-family:"Times New Roman",serif;color:#C8102E;mso-ligatures:none">Architectural Design and Optimization of Quantum-Resistant Cryptographic Processors<o:p></o:p></span></b></p>
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<b><span style="font-size:13.5pt;font-family:"Times New Roman",serif;color:black;mso-ligatures:none">Alexander Magyari</span></b><span style="font-size:13.5pt;font-family:"Times New Roman",serif;mso-ligatures:none"><o:p></o:p></span></p>
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<span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;mso-ligatures:none">April 23, 2025, 1 p.m. to 3 p.m. (CST)<br>
Location: N308-D Conference Room </span><span style="font-size:10.5pt;font-family:"Arial",sans-serif;mso-ligatures:none"><o:p></o:p></span></p>
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<b><span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;mso-ligatures:none">Committee Chair:</span></b><span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;mso-ligatures:none"><br>
Dr. Yuhua Chen, Ph.D.</span><span style="font-size:10.5pt;font-family:"Arial",sans-serif;mso-ligatures:none"><o:p></o:p></span></p>
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<b><span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;mso-ligatures:none">Committee Members:</span></b><span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;mso-ligatures:none"><br>
Dr. Jinghong Chen, Ph.D. | Dr. Xin Fu, Ph.D. | Dr. Biresh Joardar, Ph.D. | <br>
Dr. Yi-Lung Mo, Ph.D.</span><span style="font-size:10.5pt;font-family:"Arial",sans-serif;mso-ligatures:none"><o:p></o:p></span></p>
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<b><span style="font-size:12.0pt;font-family:"Arial",sans-serif;color:#C8102E;mso-ligatures:none">Abstract</span></b><span style="font-size:12.0pt;font-family:"Arial",sans-serif;color:#C8102E;mso-ligatures:none"><o:p></o:p></span></p>
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<span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;mso-ligatures:none">The rapidly growing field of quantum computing offers a wide range of improvements over classical computers across various domains. These advantages stem from various
properties of Quantum Computers, such as superposition, entanglement, and interference, which enable an exponential speed-up for specific problems when compared to Von Neumann architectures. However, this computational power also poses a critical threat to
modern cryptographic systems. Quantum algorithms such as Shor's and Grover's algorithm, both unique to quantum computers, can effectively break widely used cryptographic schemes. A new field, Post Quantum Cryptography (PQC), is quickly evolving to face the
threat of quantum computers. PQC seeks to replace current cryptographic methods, such as the AES and the RSA cryptosystems, with new algorithms that can withstand Shor's algorithm and Grover's Quantum Search Algorithm.<o:p></o:p></span></p>
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<span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;mso-ligatures:none">This dissertation explores novel hardware implementations of PQC, focusing on optimizing performance, area, and power efficiency. We present advances in cryptographic
and mathematical primitives, including low-power entropy generation techniques and hardware-optimized modular reduction beyond base-two arithmetic. Our contributions extend to power-constrained hardware, demonstrating both a Hyper Chaotic Encryptor and the
most power-efficient SPHINCS+ implementation to date. Additionally, we introduce an even lower area alternative, Ascon-Sign, specifically tailored for Internet of Things devices. Moreover, we explore how our new techniques can be used to accelerate computationally
expensive algorithms, such as Fully Homomorphic Encryption (FHE). We propose a superscalar accelerator for the Residue Number System variant of FHE, based on our new method of modular reduction, demonstrating an amortized computational throughput of 682 Gbit/s.</span><span style="font-size:10.5pt;font-family:"Arial",sans-serif;mso-ligatures:none"><o:p></o:p></span></p>
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