<html>
<head>
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
<style type="text/css" style="display:none;"> P {margin-top:0;margin-bottom:0;} </style>
</head>
<body dir="ltr">
<div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0); background-color: rgb(255, 255, 255);" class="elementToProof">
<br>
</div>
<div>
<div dir="ltr">
<div dir="ltr">
<div dir="ltr">
<div dir="ltr">
<div dir="ltr">
<div dir="ltr" class="elementToProof">
<table align="center" bgcolor="#fff" border="0" cellpadding="0" cellspacing="0" width="600" style="font-family:Arial,sans-serif">
<tbody>
<tr>
<td><img alt="Dissertation Defense Announcement at the Cullen College of Engineering" width="600" height="174" src="https://www.egr.uh.edu/sites/www.egr.uh.edu/files/enews/2022/images/thesis1.png">
<table align="center" bgcolor="#ffffff" border="0" cellpadding="10" cellspacing="0">
<tbody>
<tr>
<td align="center" style="padding:40px 20px 10px">
<div style="line-height:28px"><font color="#c8102e"><span style="font-size:24px"><b>Cost-effective Network Reordering using FPGA</b></span></font><br>
</div>
<div style="margin:30px 0px; line-height:20px">
<div style="font-size:18px; margin-bottom:5px"><strong>Vinh Hoang</strong></div>
<div style="font-size:14px; line-height:20px">
<p style="font-family:Arial,Helvetica,sans-serif; line-height:22px; margin:0px 0px 5px">
<span style="color:rgb(0,0,0)">December 2, 2022; 10:00 AM - 11:00 AM (CST)</span><br style="color:rgb(0,0,0)">
<span style="color:rgb(0,0,0)">Location: Zoom</span><br style="color:rgb(0,0,0)">
<a href="https://urldefense.com/v3/__https://uh-edu-cougarnet.zoom.us/j/98719101913?pwd=c3FMWk9qbi9BUVgrY1FNM25uNGE0QT09__;!!LkSTlj0I!FwIBFvm4uys66UTyqsqqWUoUHrLDg33-OyTKQYtXr7hrbYDgVClWoexMJWxx8lLbmkzFoFovjEaLmOtOqKQny8IYjY9xKnbA1HA$" data-auth="NotApplicable">https://uh-edu-cougarnet.zoom.us/j/98719101913?pwd=c3FMWk9qbi9BUVgrY1FNM25uNGE0QT09</a><br>
</p>
</div>
</div>
<div style="font-size:14px; line-height:20px">
<div style="color:rgb(0,0,0); line-height:20px">
<p style="margin:0px 0px 5px; font-family:Arial,Helvetica,sans-serif; line-height:22px">
<strong>Committee Chair:</strong><br>
Yuhua Chen, DSc.<br>
</p>
</div>
<div style="color:rgb(0,0,0); line-height:20px">
<p style="margin:0px 0px 20px; font-family:Arial,Helvetica,sans-serif; line-height:22px">
<strong>Committee Members:</strong><br>
Jinghong Chen, Ph.D. | Wanda Wosik, Ph.D.</p>
</div>
</div>
</td>
</tr>
<tr>
<td style="padding:0px 20px 20px">
<p style="font-family:Arial,Helvetica,sans-serif; font-size:16px; line-height:22px; margin:15px 0px; color:rgb(200,16,46)">
<strong>Abstract</strong></p>
<p style="font-family:Arial,Helvetica,sans-serif; font-size:14px; line-height:22px; margin:15px 0px">
Advancement of complex Internet of Things (IoT) devices in recent years has deepened their dependency on network connectivity, requiring robust solutions in software and hardware to achieve low latency and high throughputs. At the same time, expanding operating
conditions for these devices have brought challenges that limit the design constraints and accessibility for future hardware or software upgrades. These limitations can result in data loss because of out-of-order packets if the design specification cannot
keep up with network demands. One approach to solve this problem is to reorder packets using hardware to ease computation in other functions. Field Programmable Gate Array (FPGA) devices are ideal candidates for hardware implementations at the network entry
point due to their high performance and flexibility. This research proposes a scalable hardware-focused method for reordering packets that can be fully synthesized to FPGAs with minimal resource usage and low time complexity. The design utilizes a pipelined
approach to perform sorting in parallel and complete the operation within two clock cycles. Memory resources are optimized using a two-layer memory management system that consumes less than 1% of on-chip memory bits. Furthermore, the design is scalable to
support multi-flow applications with shared memories in a single FPGA chip.</p>
</td>
</tr>
</tbody>
</table>
</td>
</tr>
<tr>
<td><img alt="Engineered For What's Next" width="600" height="82" src="https://www.egr.uh.edu/sites/www.egr.uh.edu/files/enews/2022/images/dissertation2.png"></td>
</tr>
</tbody>
</table>
</div>
</div>
</div>
</div>
</div>
</div>
<br>
<div class="x_gmail_quote">
<div dir="ltr" class="x_gmail_attr"><br>
</div>
</div>
</div>
</body>
</html>