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<p class="x_MsoNormal"><span class="x_A0"><b><span style="font-size:16.0pt; font-family:"Calibri",sans-serif">High resolution multi-level voltage space vector structure generation for variable speed drives and grid-tied applications</span></b></span><span class="x_A4"><span style="font-size:14.0pt; font-family:"Calibri Light",sans-serif; font-weight:normal"></span></span></p>
<p class="x_MsoNormal"><img width="99" height="126" id="x_Picture_x0020_3" alt="Author_KGopakumar" tabindex="0" style="user-select: none;" data-outlook-trace="F:1|T:1" src="cid:image002.jpg@01D45BF8.CE62DE70"><span style="font-size:12.0pt"></span></p>
<p class="x_Pa0" style="margin-top:6.0pt"><img width="211" height="50" id="x__x0000_i1026" alt="Prof. K. Gopakumar
DESE, Indian Institute of Science
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<p class="x_Pa0" style="margin-top:6.0pt"><span class="x_A4"><span style="font-size:14.0pt; font-family:"Calibri",sans-serif">Wednesday, 17 Oct. 2018, 4 PM
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<p class="x_MsoNormal"><span class="x_A4"><span style="font-size:14.0pt; font-family:"Calibri",sans-serif">Room D-102, Engineering Building 1</span></span><span style="font-size:14.0pt"></span></p>
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<span style="font-family:MiloOT; color:black"><img width="156" height="32" id="x_Picture_x0020_2" tabindex="0" style="user-select: none;" data-outlook-trace="F:1|T:1" src="cid:image005.jpg@01D45BF8.CE62DE70"></span><span style="font-size:12.0pt; font-family:MiloOT"></span></p>
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<span style="font-family:"Calibri Light",sans-serif">Recently, numerous interesting multilevel topologies have been reported for motor drive applications. However, to date, the most popular topology is the neutral point clamped (NPC) three-level topology. Especially
for medium-voltage drives applications. This shows that the industry is still looking for viable alternative to this topology, with reduced power circuit complexity and increased reliability for medium-voltage drives applications. This specific lecture will
focus on some of the recent work from my lab on five-level , nine-level inverter topologies and 17-level multilevel topologies, with reduced DC-link voltages, enabling multilevel back- to- back inverter operation for medium voltage drives. This is followed
by some recent work on multilevel topologies, with stacked low voltage inverter cells, polygonal voltage space vector generation with dodecagonal, octadecagonal and 24-sided structures for variable speed drives.</span></p>
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<span style="font-family:MiloOT"><img width="156" height="29" id="x_Picture_x0020_1" tabindex="0" style="user-select: none;" data-outlook-trace="F:1|T:1" src="cid:image007.jpg@01D45BF8.CE62DE70"></span><span style="font-size:12.0pt; font-family:MiloOT"></span></p>
<p class="x_MsoNormal" style="text-align:justify"><b><span style="font-family:"Calibri Light",sans-serif">Dr. K. Gopakumar</span></b><span style="font-family:"Calibri Light",sans-serif"> (M'94-SM'96-F'11) received his B.E., M.Sc. (Engg.), and Ph.D. degrees
in Electrical Engineering from the Indian Institute of Science, Bangalore, India, in 1980, 1984, and 1994, respectively. He was with the Indian Space Research Organization, Bangalore, India from 1984 to 1987. He currently holds the position of Professor at
the Department of Electronics System Engineering, Indian Institute of Science. Dr. Gopakumar is a Fellow of IEEE, IETE India and INAE. He is currently a Co-Editor in Chief of IEEE Transactions on Industrial Electronics. He was also a Distinguished Lecturer
of IEEE Industrial Electronics Society (IES) from 2012 to 2017. His research interests include PWM converters and high power drives.</span><span style="font-size:8.0pt; font-family:"Calibri Light",sans-serif">
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