<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"><head><META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=us-ascii"><meta name=Generator content="Microsoft Word 12 (filtered medium)"><style><!--
/* Font Definitions */
@font-face
{font-family:"Cambria Math";
panose-1:2 4 5 3 5 4 6 3 2 4;}
@font-face
{font-family:Calibri;
panose-1:2 15 5 2 2 2 4 3 2 4;}
@font-face
{font-family:Tahoma;
panose-1:2 11 6 4 3 5 4 4 2 4;}
/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{margin:0in;
margin-bottom:.0001pt;
font-size:12.0pt;
font-family:"Times New Roman","serif";}
a:link, span.MsoHyperlink
{mso-style-priority:99;
color:blue;
text-decoration:underline;}
a:visited, span.MsoHyperlinkFollowed
{mso-style-priority:99;
color:purple;
text-decoration:underline;}
p.MsoAcetate, li.MsoAcetate, div.MsoAcetate
{mso-style-priority:99;
mso-style-link:"Balloon Text Char";
margin:0in;
margin-bottom:.0001pt;
font-size:8.0pt;
font-family:"Tahoma","sans-serif";}
span.BalloonTextChar
{mso-style-name:"Balloon Text Char";
mso-style-priority:99;
mso-style-link:"Balloon Text";
font-family:"Tahoma","sans-serif";}
p.emailquote, li.emailquote, div.emailquote
{mso-style-name:emailquote;
mso-margin-top-alt:auto;
margin-right:0in;
mso-margin-bottom-alt:auto;
margin-left:1.0pt;
font-size:12.0pt;
font-family:"Times New Roman","serif";}
span.EmailStyle20
{mso-style-type:personal;
font-family:"Calibri","sans-serif";
color:#1F497D;}
span.EmailStyle21
{mso-style-type:personal-reply;
font-family:"Arial","sans-serif";
color:windowtext;}
.MsoChpDefault
{mso-style-type:export-only;
font-size:10.0pt;}
@page WordSection1
{size:8.5in 11.0in;
margin:1.0in 1.0in 1.0in 1.0in;}
div.WordSection1
{page:WordSection1;}
--></style><!--[if gte mso 9]><xml>
<o:shapedefaults v:ext="edit" spidmax="1026" />
</xml><![endif]--><!--[if gte mso 9]><xml>
<o:shapelayout v:ext="edit">
<o:idmap v:ext="edit" data="1" />
</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><div><div><p class=MsoNormal align=center style='text-align:center'><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'><o:p> </o:p></span></p><p class=MsoNormal align=center style='text-align:center'><b><span style='font-family:"Arial","sans-serif";color:black'>Thursday, August 9, 2012</span></b><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'><o:p></o:p></span></p><p class=MsoNormal align=center style='text-align:center'><b><span style='font-family:"Arial","sans-serif";color:black'>N355-D – 10:15 AM</span></b><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'><o:p></o:p></span></p><p class=MsoNormal align=center style='text-align:center'><b><span style='font-size:18.0pt;font-family:"Arial","sans-serif";font-variant:small-caps;color:black'>Nanoelectronics – Device and Circuit Interactive Design and Optimization</span></b><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'><o:p></o:p></span></p><p class=MsoNormal align=center style='text-align:center'><span style='font-size:10.0pt;font-family:"Arial","sans-serif";color:black'>Dr. Lan Wei</span><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'><o:p></o:p></span></p><p class=MsoNormal align=center style='text-align:center'><span style='font-size:10.0pt;font-family:"Arial","sans-serif";color:black'>Microsystems Technology Laboratories, Massachusetts Institute of Technology</span><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'><o:p></o:p></span></p><p class=MsoNormal style='text-align:justify'><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'> <o:p></o:p></span></p><p class=MsoNormal style='text-align:justify'><b><u><span style='font-size:10.0pt;font-family:"Arial","sans-serif";color:black'>Abstract</span></u></b><span style='font-size:10.0pt;font-family:"Arial","sans-serif";color:black'>: Nowadays, physical gate length can no longer be effectively scaled down and traditional boosters (e.g., strain, high-k/metal gate) are having diminishing return. Continued progress in nanoelectronics necessitates a holistic view across the boundaries of device, circuit and system. Device engineering and circuit design must be interactively explored targeting improvement at circuit and system level, while the new applications in various areas are enabled by emerging technology. </span><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'><o:p></o:p></span></p><p class=MsoNormal style='text-align:justify'><span style='font-size:10.0pt;font-family:"Arial","sans-serif";color:black'>In this talk, the design space is explored for future Si CMOS technology, and carbon nanotube field effect transistor, a promising technology in the post-Si era. Compact models of transport properties and capacitive components of different device structures have been developed to fascinate circuit-level analysis and system-level optimization. Opportunities and challenges are discussed along the path of continuing technology scaling. Possible ways of extending technology roadmap are proposed. We propose scenarios of selective device structure scaling that will enable Si CMOS technology scaling for several generations beyond the currently perceived limits. Beyond Si CMOS scaling, carbon nanotube field effect transistors (CNFETs) are optimized and projected to achieve 5x chip-level speed up over PDSOI with the same power constraints at 11 nm technology node for a high-performance four-core processor with 1.5M logic gates and 5MB SRAM per core. A new benchmarking methodology for an <i>apples-to-apples</i> comparison among different device structures is proposed, which also links the device-level behaviors and circuit-level performance and energy efficiency. The methodology is further extended into an optimizing tool for device/circuit interactive design.</span><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'><o:p></o:p></span></p><p class=MsoNormal style='text-align:justify'><span style='font-size:10.0pt;font-family:"Arial","sans-serif";color:black'> </span><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'><o:p></o:p></span></p><p class=MsoNormal style='text-align:justify'><b><u><span style='font-size:10.0pt;font-family:"Arial","sans-serif";color:black'>Short Bio</span></u></b><span style='font-size:10.0pt;font-family:"Arial","sans-serif";color:black'>:</span><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'><o:p></o:p></span></p><div style='margin-top:5.0pt;margin-bottom:5.0pt'><p class=MsoNormal style='text-align:justify'><span style='color:black'> </span><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'><o:p></o:p></span></p></div><div style='margin-top:5.0pt;margin-bottom:5.0pt'><p class=MsoNormal style='text-align:justify'><span style='font-size:10.0pt;font-family:"Arial","sans-serif";color:black'>Lan Wei received her B. S. in Microelectronics and Economics from Peking University, Beijing, China in 2005 and M. S. and Ph. D. in Electrical Engineering from Stanford University, Stanford, USA in 2007 and 2010, respectively. She is currently a post-doctoral associate in Microsystems Technology Laboratories, Massachusetts Institute of Technology. Her research focuses on technology scaling from circuit-level and chip-level perspectives, device/circuit interactive design, as well as integrated bio-system. She worked as a research intern at Intel (2006), IBM Research (2007), STMicroelectronics (2008), and the Grenoble Institute of Technology (2008). </span><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'><o:p></o:p></span></p></div><div style='margin-top:5.0pt;margin-bottom:5.0pt'><p class=MsoNormal style='text-align:justify'><span style='font-size:10.0pt;font-family:"Arial","sans-serif";color:black'>Lan has authored or co-authored more than 30 technical papers. She has served on the Technical Program Committee of the International Electron Devices Meeting (<i>IEDM</i>) since 2011, and has been a reviewer for several <i>IEEE</i> and <i>ACM</i> journals since 2006. She was one of the key contributors to the Process Integration, Devices, and Structures (<i>PIDS</i>) Chapter of the International Technology Roadmap for Semiconductors (<i>ITRS</i>) 2009 Edition. </span><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'><o:p></o:p></span></p></div><p class=MsoNormal style='text-align:justify'><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'> <o:p></o:p></span></p><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif";color:black'> <o:p></o:p></span></p></div></div></div></div></body></html>