[CCoE Notice] Cullen College Dissertation Defense Announcement - Hao Deng

[Hutchinson, Inez A]

[Image]

Power-Efficient High-Speed Time-Domain Hybrid SAR ADCs

Hao Deng

December 6, 2023; 10:00 AM - 12:00 PM (CST)
Location: ECE Conference Room, Engineering Building I
Zoom: Meeting ID: 912 4746 4908; Passcode: 940293

Committee Chair:
Jinghong Chen, Ph.D.

Committee Members:
Jiming Bao, Ph.D. | Yuhua Chen, Ph.D. | Biresh Kumar Joardar, Ph.D. | Larry Yi-Lung Mo, Ph.D. | David R. Jackson, Ph.D.

Abstract

Medium-to-high resolution Analog-to-Digital Converters (ADCs) are pivotal in diverse applications such as test instrumentation, wireline transceivers, and wireless communication infrastructures. Successive-Approximation-Register (SAR) ADCs have become popular due to their energy efficiency and advancements, especially in the CMOS technology with a channel length under 65 nm. However, SAR ADCs face limitations in signal-to-noise ratio (SNR), mainly due to comparator thermal noise. Time-Domain Hybrid SAR ADCs have been developed to improve SNR while maintaining its power efficiency, but they have longer conversion times. This research focuses on the system and circuit level innovations to enhance the sampling rate of time-domain hybrid SAR ADCs without sacrificing their power efficiency and SNR benefits.

The first innovation is a SAR-assisted Two-Step Digital-Slope ADC, specifically a 6-bit two-step digital slope second stage that increases conversion speed by 41.7% compared to conventional digital slope ADCs. Utilizing 55 nm CMOS technology, this ADC achieves a 56.27 dB Signal-to-Noise-Distortion Ratio (SNDR) at 400 MS/s, with a power consumption of 2.4 mW. This leading to a Walden Figure of Merit (FOM) of 11.24 fJ/conv.-step. The second innovation is an 8-Channel Time-Interleaved (TI) Time-to-Digital Converter (TDC)-assisted SAR ADC. This design includes a latch-based Voltage-to-Time Converter (VTC) and a Linear Time-Domain Amplifier (TA) to improve voltage-to-time conversion speed and time-domain quantization accuracy. A 5-bit Flash TDC with non-uniform delay cells is used in the second stage to enhance overall speed and equalize the VTC non-linearities. Fabricated in Global Foundry's 22 nm Fully-Depleted Silicon-On-Insulator (FD-SOI) CMOS technology, this silicon validated ADC prototype achieves an measurement result of 8.4-bit Effective Number of Bits (ENOB) at 5 GS/s, leading to a Walden FOM of 43.59 fJ/conv.-step.

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